This invention relates to the fabrication of microminiature devices such as fine-line semiconductor integrated-circuit devices and, more particularly, to achieving and/or evaluating alignment between lithographic masks or reticles and an associated wafer in which devices are formed.
A typical fabrication sequence for making integrated-circuit devices involves successively defining fine-line features on a resist-coated semiconductive wafer. For some fine-line devices, resolution down to or below the 1-micrometer (.mu.m) level, with overlay accuracy from level to level of only about .+-.0.125 .mu.m or better, is required. Each step of the fabrication sequence therefore requires accurate positioning of a mask or reticle with respect to the wafer, as is well known in the art.
Fiducial marks on the mask or reticle and on the wafer are typically utilized to establish alignment therebetween. Moreover, as a basis for evaluating critical level-to-level alignments that are actually achieved, a so-called vernier pattern is typically formed on the wafer. Examination of this pattern gives a visual indication of the actual alignment accuracy realized on the wafer between specified levels during the fabrication sequence.
Various types of marks have been successfully employed for alignment purposes in integrated-circuit device fabrication. As, however, the dimensions of these devices continue to decrease, the ability of a human operator to rapidly determine the relative orientation of standard alignment marks with sufficiently high precision becomes increasingly difficult.
Accordingly, efforts have been directed by workers in the integrated-circuit device art aimed at trying to devise improved alignment marks. It was recognized that such efforts, if successful, had the potential for decreasing the time required by an operator to achieve and/or to evaluate level-to-level alignment in a fine-line device fabrication sequence. In turn, this would lower the cost and improve the quality of devices made utilizing such marks.